The "bondPad" cell contains a number of implicit connections, as well as the explicit I/O connection. There is a ground plane connection as well as the usual substrate connection for SiGeHP devices. Being implicitly defined, if your design enviroment doesn't match the assumptions of the design kit builders you will not only be misconnected but you won't know it until you try to simulate or verify.
The assumed scenario is CMOS with a positive supply. (Strangely, the ground plane node is in places called "back node" and connected to "vdd!", not "gnd!".)This is obviously a problem for us since we are designing circuits with bipolar devices and a negative supply.
Luckily, there are alternative symbols that provide explicit connections for these nodes. bondPadx provides an explicit ground plane connections, and bondPadxx provides both a ground plane and a substrate connection. (In general, the "x" form of a cell provides the explicit substrate connection.)
Note that is only for the connectivity in the schematic. Tying down the ground plane in the layout is another matter...
3:17:25 PM  Categories: Cadence Knowledge-log
|
