Intel stretching silicon for power. CNET Aug 12 2002 11:15PM ET [Moreover - moreover...]
0.09 um, strained-silicon, low-k field dielectric, seven-layer metalization, 12-inch wafers.
Although... these days it's so hard to tell whay dimension is refered to when citing a process. It seems to be what ever is convenient to advance the purpose of the press release. (The article does say gate length will be 0.05 um.)
I've had at least one long arguement withmy thesis advisor that two layers of SiO2 is 5 "atoms" thick. He insists that it must be 6, and therefore any mention of 5 must be totaly "fake".
Heck, I don't even do CMOS anyway. Can't remeber the last time I did either.
6:16:26 PM  Categories: Pushing rectangles...
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